A group III nitride semiconductor, whose typical examples are gallium nitride (GaN), AlGaN, InGaN, and the like, is advantageous as a material. As such, in a case where the group III nitride semiconductor is used as a power device, it is possible to anticipate good device properties such as high withstand voltage, high-speed operation, high heat-resistance, and low on-resistance. Because of this, in place of a conventional Si-material power device whose properties as a power device have come close to the limit, development of a power device in which the group III nitride semiconductor is utilized has been conducted.
Particularly, with regard to a field-effect transistor (FET), a transistor with a high electron mobility can be realized by causing a high-density two dimensional electron gas (2DEG) to be formed near a heterojunction interface between, for example, AlGaN and GaN. That is, it is possible to further reduce an on-resistance of the FET. There have been provided various device structures in which such a heterojunction interface is utilized.
Such a GaN FET is usually of a normally-on type which has a negative threshold voltage and, when a gate voltage is 0 V (zero volt), is brought into an on-state, in which a drain current flows.
In contrast, as to, for example, a metal-oxide semiconductor field-effect transistor (MOSFET) and an insulated gate bipolar transistor (IGBT), a normally-off type is the mainstream. A normally-off type transistor has a positive threshold voltage and, when a gate voltage is 0 V, is brought into an off-state, in which no drain current flows.
A normally-on type GaN FET has good properties such as high withstand voltage, high-speed operation, high heat-resistance, and low on-resistance. However, since it is necessary to supply a negative voltage to a gate in the normally-on type GaN FET, presence of a negative voltage supply source causes an increase in cost and an increase in circuit size in a case where the normally-on type GaN FET is used.
In order to use a GaN FET as a normally-off type FET, it is necessary to connect a normally-on type field-effect transistor with a normally-off type MOSFET by a connection technique called cascode connection. A power semiconductor device, in which a normally-off operation is achieved in this manner, has been well known. Since a MOSFET with low withstand voltage can be used as the normally-off type MOSFET, it is possible to minimize an increase in cost and a deterioration in property.
For example, Non-patent Literature 1 discloses a method of controlling, for the purpose of achieving EMC (electromagnetic compatibility), dv/dt in a cascode circuit in which a normally-on type SiC JFET (Junction Field-Effect Transistor) is cascode-connected with a MOSFET. Specifically, Cdg, M is added as illustrated in (a) of FIG. 9 or (i) Rd, (ii) Cdg, J, and (iii) Rgs are added as illustrated in (b) of FIG. 9, so that a time constant of a negative feedback at the time of a switching operation is changed. Thus dv/dt is controlled.
Note that Cdg, M in a circuit diagram illustrated in (a) of FIG. 9 and (i) Cdg, J and (ii) Rgs in a circuit diagram illustrated in (b) of FIG. 9 are variable because of an experiment for showing that dv/dt can be controlled by causing a capacitance or a resistance to change. Cdg, M, Cdg, J, and Rgs do not have to be variable. By determining, at the time of designing, the time constant of the negative feedback appropriately in accordance with a drain-gate capacitance or an internal gate resistance, a voltage change rate dv/dt which provides a good balance between (i) electric power efficiency which varies in accordance with switching loss and (ii) noise is achieved.
Non-patent Literature 2 discloses a cascode circuit in which a normally-on type SiC JFET is cascode-connected with a MOSFET. It is also disclosed that a reverse recovery current, which flows in a direction from a drain to a source when an electric current in a direction from the source toward the drain is shut off, is large in the cascode circuit. Non-patent Literature 2 further discloses a control method for preventing a large reverse current, as well as a control method which is employed in a circuit different from the cascode circuit.
Further, Patent Literature 1 discloses a semiconductor device which can achieve a normally-off operation and prevent an increase in manufacturing cost.
Still further, Patent Literature 2 discloses a power semiconductor device which reduces a switching loss caused by a reverse recovery current.